Field of the Invention
The invention relates to a memory device having at least one capacitor device, which is configured for storing information on the basis of a hysteresis process and which has for this purpose a first and a second electrode, first and second terminals connected thereto, and also an influence region with an influence medium provided between the electrodes. At least one transistor device is provided, and is configured for accessing the capacitor device for the purpose of reading and changing the information and which is connected to the capacitor device. At least one plate line device is electrically conductively connected to the capacitor device through a free terminal and is configured for sensing the electromagnetic state of the capacitor device with a sense amplifier device in order to access the information stored there.
In the development of modern memory technologies, it is necessary simultaneously to fulfill different, in part initially conflicting boundary conditions in order to configure an effective memory module which can then also be developed cost-effectively and disseminated commercially. These fundamental requirements relate to the geometrical extent, the switching speeds and also the complexity of the layout that is then to be realized in the semiconductor substrate and forms the basis of the respective memory module or of the individual memory cell.
In memory devices, memory cells are usually disposed in matrix form and are activated by simultaneous addressing via an assigned row or word line and an assigned column or bit line in order to be read from and/or written to. In accordance with the activation, e.g. a capacitor or the like which is configured to store information is then accessed. Conventional access is essentially effected via a transistor which can be connected or is connected to the capacitor, to be precise by a procedure in which, after activation, the information-carrying signal to be read out on the capacitor is detected by a corresponding sense amplifier in the column line or bit line and correspondingly amplified in order then to be forwarded in a manner such that it can be tapped off as an amplified data signal.
Further requirements made of the memory mechanism, in particular the aim of simplifying the memory management and the desire to maintain the memory contents independently of an operating voltage, have motivated so-called nonvolatile memory technologies. The latter are based e.g. essentially on a hysteresis process or effect in the memory element or storage capacitor. These aspects are manifested for example in the development of so-called FeRAM cells, MRAM cells or the like.
Memory cells of the nonvolatile type, in particular FeRAM cells or the like, are usually connected between one of the column lines or bit lines and an additional charging line, also referred to as plate line or “plate”. The plate line is usually connected to a driver circuit, which holds the plate line at a predetermined potential. During conventional operation of the memory device, the column lines or bit lines and the charging lines or plate lines of the memory device in each case have an active and an inactive operating mode or corresponding state. In the active operating mode, in which, by way of example, the content of a memory cell is read out, the corresponding column line or bit line is connected to a sense amplifier. The plate line or charging line is at a predetermined potential in this case. In the inactive operating mode, the corresponding column lines or bit lines and the respective charging lines are generally connected to a terminal for a common supply potential, in particular in order to avoid unintentional alterations of the memory content, for example due to disturbances or the like.
Despite these developments, there is still nevertheless the need for a higher integration of the individual memory cells in the semiconductor substrate and for the shortening of switching times. At the same time, overall, for the realization of these concepts, the layout of the respective lines with respect to the individual memory cells in the entire memory module is to be configured with a particularly low area requirement.